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general description the max4959/max4960 overvoltage protection con- trollers protect low-voltage systems against high-volt- age faults of up to +28v. when the input voltage exceeds the overvoltage lockout (ovlo) threshold, these devices turn off an external pfet to prevent dam- age to the protected components. the undervoltage lockout (uvlo) threshold holds the external pfet off until the input voltage rises to the correct level. an addi- tional safety feature latches off the pfet when an incor- rect low-power adapter is plugged in. the max4959/max4960 control an external battery switchover pfet (p2) (see figures 4 and 6) that switches in the battery when the ac adapter is unplugged. the undervoltage and overvoltage trip levels can be adjusted with external resistors. the input is protected against ?5kv hbm esd when bypassed with a 1? ceramic capacitor to ground. all devices are available in a small 10-pin (2mm x 2mm) ?fn and 10-pin ?ax packages and are specified for operation over the extended -40? to +85? temperature range. applications notebooks laptops camcorders ultra-mobile pcs features overvoltage protection up to +28v 2.5% accurate externally adjustable ovlo/uvlo thresholds battery switchover pfet control protection against incorrect power adapter low (100? typ) supply current 25ms input debounce timer 25ms blanking time 10-pin (2mm x 2mm) ?fn and 10-pin ?ax packages max4959/max4960 high-voltage ovp with battery switchover ________________________________________________________________ maxim integrated products 1 19-0874; rev 0; 7/07 for pricing delivery, and ordering information please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin- package top mark pkg code max4959 elb+ -40c to +85c 10 dfn aao l1022-1 MAX4959EUB+* -40c to +85c 10 max u10-1 max4960 elb+ -40c to +85c 10 dfn aap l1022-1 max4960eub+* -40c to +85c 10 max u10-1 123 10 9 8 45 76 gate2 gnd v dd n.c. gate1 ovs in n.c. (source1) max4959 max4960 dfn top view cb uvs + 1 2 3 4 5 6 7 8 9 10 gate2 gnd v dd n.c. gate1 ovs ( ) max4960 only. in n.c. (source1) max4959 max4960 max cb uvs + pin configurations typical operating circuits appear at end of data sheet. + denotes a lead-free package. * future product?ontact factory for availability.
max4959/max4960 high-voltage ovp with battery switchover 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = +19v, t a = -40? to +85?, unless otherwise noted, c vdd = 100nf. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, source1, gate1, gate2, to gnd ................-0.3v to +30v v dd to gnd ..............................................................-0.3v to +6v uvs, ovs, cb to gnd .............................................-0.3v to +6v continuous power dissipation (t a = +70?) 10-pin ?fn (derate 5.0mw/? above +70?) ...........403mw 10-pin ?ax (derate 5.6mw/? above +70?) ...........444mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units in input voltage range v in 428v overvoltage adjustable trip range ovlo (note 2) 6 28 v overvoltage comp reference ov ref v in rising edge 1.18 1.228 1.276 v ovs input leakage current ovi lkg -100 +100 na overvoltage trip hysteresis ov hys 1% undervoltage adjustable trip range uvlo (note 2) 5 28 v undervoltage comp reference uv ref v in falling edge 1.18 1.228 1.276 v uvs input leakage current uvi lkg -100 +100 na undervoltage trip hysteresis uv hys 1% internal undervoltage trip level intuv ref v in falling edge 4.1 4.4 4.7 v internal undervoltage trip hysteresis intuv hys 1% power-on trip level potl v dd > +3v, in rising edge 0.5 0.75 1 v power-on trip hysteresis potl hys 10 % in supply current i in v in = +19v, v ovs < ov ref and v uvs > uv ref 100 300 ? v dd v dd voltage range v dd 2.7 5.5 v v dd undervoltage lockout v dduvlo v dd falling edge 1.55 2.40 v v dd undervoltage lockout hysteresis v d d uv lohy s 50 mv v dd supply current i vdd v dd = +5v, v in = 0v 10 ? gate_ gate1 open-drain mos r on resistance r on v cb = 0v, v in = 19v, v ovs < ov ref and v uvs > uv ref , i gate_ = 0.5ma (max4959) 1k gate2 open-drain mos r on resistance r on v cb = 3v, i gate_ = 0.5ma 1 k
max4959/max4960 electrical characteristics (continued) (v in = +19v, t a = -40? to +85?, unless otherwise noted, c vdd = 100nf. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units gate1 leakage current g1i lkg v ov s > ov r e f , v u v s < u v r e f , or v c b = + 5v -1 +1 ? gate2 leakage current g2i lkg v cb = 0v -1 +1 ? cb logic-level high v ih 1.5 v logic-level low v il 0.4 v cb pulldown resistor r cbpd 123m timing debounce time t deb v ovp > v in > v uvp for greater than t deb for gate1 to go low 10 25 40 ms gate1 assertion delay from cb pin t1 gate cb = +3v to 0 rise time = fall time = 5ns (note 3) 50 ns gate2 assertion delay from cb pin t2 gate cb = 0 to +3v rise time = fall time = 5ns (note 3) 50 ns blanking time t blank 10 25 40 ms max4960 source1/gate1 resistance r sg (max4960) 140 200 260 k gate1/ground resistance r gg gate1 asserted (max4960) 140 200 260 k note 1: operation is tested at t a = +25 c and guaranteed by design for ?fn package. operation over specified temperature range is tested for ?ax package. note 2: do not exceed absolute maximum rating; the ratio between the externally set ovlo and uvlo threshold must not exceed 4, [ovlo/uvlo] max 4. note 3: assertion delay starts from switching of cb pin to reaching of 80% of gate1/gate2 transition. this delay is measured without external capacitive load. high-voltage ovp with battery switchover _______________________________________________________________________________________ 3 power-up response (r pullup = 1k ) max4959/60 toc01 time ( s) voltage (v) 100 50 0 -50 -100 0 2 4 6 8 10 12 -2 -150 150 v in v dd v gate1 overvoltage response (r pullup = 5k ) max4959/60 toc02 time ( s) voltage (v) 100 50 0 -50 -100 5 10 15 20 25 30 0 -150 150 v in v dd v gate1 undervoltage response (within blanking time) (r pullup = 1k ) max4959/60 toc03 time ( s) voltage (v) 60 50 10 20 30 40 2 4 6 8 10 12 14 16 0 070 drain of p1 v in v gate1 typical operating characteristics (v ovlo = 22.2v and v uvlo = 10.1v, r1 = 887k , r2 = 66.5k , r3 = 54.9k , all resistors 1%, ov ref = uv ref = 1.228v.)
max4959/max4960 high-voltage ovp with battery switchover 4 _______________________________________________________________________________________ low-power adapter response (v ovlo = 22.3v, v uvlo = 10.1v, pfet = irf7726 ) max4959/60 toc04 time (s) voltage (v) 0.25 0.2 0.15 0.1 .05 1 3 5 7 9 11 13 -1 0 0.3 load becomes present drain of p1 v in v gate1 battery switchover with adapter- plugged response (v in = 19v, v gate2-pullup = 4.2v, r pullup = 5k ) max4959/60 toc05 time ( s) voltage (v) 100 50 0 -50 -100 0 5 10 15 20 25 -5 -150 150 v gate1 v gate2 cb overvoltage and undervoltage trip difference vs. temperature (r pullup = 1k ) max4959/60 toc06 temperature ( c) voltage (v) 70 50 30 10 -10 -30 -4 -3 -2 -1 0 1 2 3 4 5 -5 -50 90 uv trip diff ov trip diff supply current vs. input voltage max4959/60 toc07 v in (v) i supp ( a) 25 20 15 10 5 0 40 80 120 160 200 -40 0 logic-input threshold vs. temperature max4959/60 toc08 temperature ( c) logic threshold (v) 90 70 30 50 -10 10 -30 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 -50 v th-lo v th-hi v dd supply current vs. temperature max4959/60 toc09 temperature ( c) v dd supply current ( a) 90 70 50 30 10 -10 -30 4 4.5 5 3.5 -50 110 voltage range vs. input voltage range max4959/60 toc10 v in (v) v dd (v) 10 525 15 20 1 2 3 4 5 6 0 0 typical operating characteristics (continued) (v ovlo = 22.2v and v uvlo = 10.1v, r1 = 887k , r2 = 66.5k , r3 = 54.9k , all resistors 1%, ov ref = uv ref = 1.228v.)
detailed description the max4959/max4960 provide up to +28v overvoltage protection for low-voltage systems. when the input volt- age exceeds the overvoltage trip level, the max4959/ max4960 turn off an external pfet to prevent damage to the protected components. the max4959/max4960 feature a control bit (cb) pin that controls an external battery-switchover function that switches in the battery when the adapter is unconnect- ed. the host system detects when the battery switchover must take place and pulls cb high to turn on p2. the load current is not interrupted during battery switchover as the body diode of p2 conducts until the cb line is dri- ven high (see the max4959 typical operating circuit 1 , figure 4). an additional safety feature latches off pfet p1 when a low-power adapter is plugged in. this protects the sys- tem from seeing repeated adapter insertions and removals when an incorrect low-power adapter is plugged in that cannot provide sufficient current. undervoltage lockout (uvlo) the max4959/max4960 have an adjustable undervolt- age lockout threshold ranging from +5v to +28v. when v in is less than the v uvlo , the device waits for a blank- ing time, t blank , to see if the fault still exists. if the fault does not exist at the end of t blank , p1 remains on. if v in is less than v uvlo for longer than the blanking time, the device turns p1 off and p1 does not turn on again until v in < 0.75v. see figure 1. overvoltage lockout (ovlo) the max4959/max4960 have an adjustable overvolt- age lockout threshold ranging from +6v to +28v. when v in is greater than the v ovlo , the device turns p1 off immediately. when v in drops below v ovlo, p1 turns on again after the debounce time has elapsed. device operation high-voltage adapter (v in > v ovlo ) if an adapter with a voltage higher than v ovlo is plugged in, the max4959/max4960 is in an ovp condi- tion, so p1 is kept off or immediately turned off. there is max4959/max4960 high-voltage ovp with battery switchover _______________________________________________________________________________________ 5 pin description pin max4959 max4960 name function 1 1 gate1 pfet gate drive output open drain. gate1 is actively driven low, except during fault (ovp or uvp) condition (the external pfet is turned off). when v uvlo < v in < v ovlo , gate1 is driven low (the external pfetp1 is turned on). 2, 9 9 n.c. no connection. not internally connected. (connect to ground or leave unconnected.) ? source1 pfet source output. an internal resistor is connected between source1 and gate1. 33in voltage input. in is both the power-supply input and the overvoltage/undervoltage sense input. bypass in to gnd with a 1? ceramic capacitor to get a ?5kv protected input. a minimum 0.1? ceramic capacitor is required for proper operation. 4 4 uvs undervoltage threshold set input. connect uvs to an external resistive divider from in to gnd to set the undervoltage lockout threshold. (see typical operating circuits .) 5 5 ovs overvoltage threshold set input. connect ovs to an external resistive divider from in to gnd to set the overvoltage lockout threshold. (see typical operating circuits .) 66v dd inter nal p ow er - s up p l y outp ut. byp ass v d d to gn d w i th a 0.1f m i ni m um cap aci tor . v d d p ow er s the i nter nal p ow er - on r eset ci r cui ts. ( s ee the v d d c ap aci tor s el ecti on secti on.) 77cb battery switchover control input. when cb is high, gate1 is high (p1 is off), and gate2 is low (p2 is on). when cb is low, gate1 is controlled by internal logic and gate2 is high (p2 is off). gate1 is controlled by cb only if v ulo < v in < v ovlo . 8 8 gnd ground 10 10 gate2 pfet gate drive output, open drain. when cb is high, gate2 is low (p2 is on). when cb is low, gate2 is high impedance (p2 is off).
max4959/max4960 no blanking time for ovp, but the debounce time applies once the in voltage falls below v ovlo but above v uvlo . when the voltage at in is higher than v ovlo , the cb pin does not control p1. correct adapter (v uvlo < v in < v ovlo ) in this case, when the adapter is plugged in, the device goes through a 20ms (typ) debounce time and ensures that the voltage at in is between v uvlo and v ovlo before p1 is turned on. in this state, the cb pin controls both p1 and p2. low-power adapter or glitch condition if the adapter has the correct voltage but not enough power (incorrect low-power adapter), the max4959/ max4960 protect pfet p1 from oscillation. when the adapter is first plugged in, p1 is off so the voltage is cor- rect. when p1 is turned on after the debounce time, the low-power adapter is dragged down to below v uvlo . the device waits for a 10ms blanking time to make sure it is not a temporary glitch, and, if a fault still exists, it latches off p1. p1 does not turn on again until the adapter is unplugged (v in <~0.75v) and plugged in again. this feature can work without the battery present high-voltage ovp with battery switchover 6 _______________________________________________________________________________________ max4959 + - + - + - + - gate2 cb gnd uvs ovs v dd n2 n1 gate1 n in v sg + - + - logic digital supply analog supply bandgap uvlo ovlo uvloint power on v dd uvlo vref1 = 2v vref2 = 0.7v power-on reset and off storage functional diagram for the max4959 functional diagrams
only if the backup capacitor on v dd is large enough to maintain power for greater than the 10ms blanking time. the detection that the adapter is unplugged and plugged in again is implemented by monitoring the v in signal. the adapter is unplugged when v in drops below v in =~ 0.75v, and it is plugged in when v in becomes greater than v in =~ 0.75v. to ensure the monitoring of this lower threshold, an external storage capacitor at the v dd pin is necessary. when the input voltage v in drops below 4v, power for some internal v in monitoring circuit- ry is supplied by the external capacitor at the v dd pin. this capacitor is supplied by v in through a diode and is internally limited to 5.5v. adapter not present (v in < v uvlo ) when the input voltage v in drops below 4.4v, p1 is turned off automatically and p1 does not turn on again until the adapter is unplugged (v in <~0.75v) and plugged in again. when the adapter is not present, p1 is kept off with the gate-source resistor (which is internal for the max4960 and external for the max4959), and the cb pin controls the battery switchover pfet p2. max4959/max4960 high-voltage ovp with battery switchover _______________________________________________________________________________________ 7 max4960 + - + - + - + - gate2 cb gnd uvs ovs v dd n2 n1 gate1 source1 n in v sg + - + - logic digital supply analog supply bandgap uvlo ovlo uvloint power on v dd uvlo vref1 = 2v vref2 = 0.7v power-on reset and off storage functional diagram for the max4960 functional diagrams (continued)
max4959/max4960 high-voltage ovp with battery switchover 8 _______________________________________________________________________________________ v in v ovlo v ovlo v uvlo v dd regulated t deb t deb t blank t blank t deb v uvlo intuv ref v gate1 v dd v cb v gate2 figure 1. timing diagram in range p1 state p2 state v in > v ovlo p1 off (not affected by cb) v uvlo < v in < v ovlo (debounce timeout ongoing) p1 off (not affected by cb) v uvlo < v in < v ovlo (debounce timeout elapsed) cb = 1 -> p1 is off cb = 0 -> p1 is on v intuvref < v in < v ovlo (blanking timeout ongoing) cb = 1 -> p1 is off cb = 0 -> p1 is on v intuvref < v in < v ovlo (blanking timeout elapsed) p1 off (not affected by cb). p1 does not turn on again until adapter is unplugged (v in <~0.75v) and plugged in again. v in < v intuvref p1 off (not affected by cb). p1 does not turn on again until adapter is unplugged (v in <~0.75v) and plugged in again. cb = 1 -> p2 is on cb = 0 -> p2 is off the following table lists the different modes of operations:
applications information mosfet configuration and selection the max4959/max4960 are used with a single mos- fet configuration as shown in the typical operating circuits to regulate voltage as a low-cost solution. the max4959/max4960 are designed with pfets. for lower on-resistance, the external mosfet can be multi- ple pfets in parallel. in most situations, mosfets with r ds(on) specified for a v gs of 4.5v work well. also, mosfets (with v ds 30v) withstand the full +28v in range of the max4959/max4960. resistor selection for overvoltage/undervoltage window the max4959/max4960 include undervoltage and overvoltage comparators for window detection (see figure 4). gate1 is enhanced and after the debounce time, the pfet is turned on when the monitored voltage is within the selected window. the resistor values r1, r2, and r3 can be calculated as follows: where r total = r1 + r2 + r3. use the following steps to determine the values for r1, r2, and r3: 1) choose a value for r total , the sum of r1, r2, and r3. because the max4959/4960 have very high input impedance, r total can be up to 5m . 2) calculate r3 based on r total and the desired v ovlo trip point: 3) calculate r2 based on r total , r3, and the desired v uvlo trip point: 4) calculate r1 based on r total , r2, and r3: r1 = r total ?r2 ?r3 note that the ratio between the externally set ovlo and uvlo threshold must not exceed: 4 [v ovlo / v uvlo ] max 4) v dd capacitor selection v dd is regulated to +5v by a linear regulator. since the minimum external adjustable uvlo trip threshold is +5v, the v dd range is +5v to +28v and the value at v dd is: v dd = v in ?0.8v where v in = 5v to 5.8v v dd = +5v where v in > 5.8v the capacitor at v dd must be large enough to provide power to the device for an external settable time, t hold , when v in drops to 0v. the capacitor value to have a minimum time of t hold is: c = (i vdd x t hold ) / (v dd - v dd uvlo) the worst case scenario is where v in = +5v, v dd = v in - 0.8v = +4.2v, i vdd = 10? (max). for a t hold time of 20ms, c = (10? x 20ms) / (4.2v - 2.2v) = 100nf. note: the capacitor must be greater than 100nf for the internal regulator to be stable, and needs to have low esr and low leakage current, for example, a ceramic capacitor. in bypass considerations for most applications, bypass in to gnd with a 1? ceramic capacitor. if the power source has significant inductance due to long lead length, take care to pre- vent overshoots due to the lc tank circuit, and provide protection if necessary to prevent exceeding the +30v absolute maximum rating on v in . the max4959/max4960 provide protection against volt- age faults up to+28v, but this does not include negative voltages. if negative voltages are a concern, connect a schottky diode from in to gnd to clamp negative input voltages. esd test conditions the max4959/max4960 are protected from ?5kv human body model esd on in when in is bypassed to ground with a 1? ceramic capacitor. human body model figure 2 shows the human body model and figure 3 shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of interest that is then discharged into the device through a 1.5k resistor. r ur ref total uvlo 23 = ? ? ? ? ? ? ? v v r r or ref total ovlo 3 = v v vu r r vo r uvlo ref total ovlo ref total = () + ? ? ? ? ? ? = () ? ? ? ? ? ? v r v r 23 3 max4959/max4960 high-voltage ovp with battery switchover _______________________________________________________________________________________ 9
max4959/max4960 chip information process: bicmos high-voltage ovp with battery switchover 10 ______________________________________________________________________________________ charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m r d 1.5k high- voltage dc source device under test figure 2. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 3. human body current waveform
max4959/max4960 high-voltage ovp with battery switchover ______________________________________________________________________________________ 11 typical operating circuits p1 cb v ref gnd r1 r2 r3 n2 v dd 1-cell (4.2v) to 4-cell (16.8v) rd1 n1 ru1 c1 d1 c2 ru2 p2 rd2 gate2 gate1 in uvlo ovlo uvs ovs ac adapter hold-up power supply logic dc-dc converter battery charger v supply figure 4. max4959 typical operating circuit 1
max4959/max4960 high-voltage ovp with battery switchover 12 ______________________________________________________________________________________ typical operating circuits (continued) cb 3.3v gnd r1 r2 r3 n2 v dd 1-cell (4.2v) to 4-cell (16.8v) n1 gate2 gate1 in uvlo rd1 ovlo uvs ovs ac adapter hold-up power supply logic dc-dc converter system load en v ref v supply 28v protected charger figure 5. max4959 typical operating circuit 2
max4959/max4960 high-voltage ovp with battery switchover ______________________________________________________________________________________ 13 typical operating circuits (continued) p1 cb gnd r1 r2 r3 n2 v dd 1-cell (4.2v) to 4-cell (16.8v) n1 c1 c2 ru2 p2 rd2 gate2 gate1 source1 in uvlo ovlo uvs ovs ac adapter hold-up power supply logic dc-dc converter battery charger v ref v supply figure 6. max4960 typical operating circuit 1
max4959/max4960 high-voltage ovp with battery switchover 14 ______________________________________________________________________________________ typical operating circuits (continued) cb gnd r1 r2 r3 n2 v dd 1-cell (4.2v) to 4-cell (16.8v) n1 gate2 gate1 in uvlo ovlo uvs ovs ac adapter hold-up power supply logic dc-dc converter battery charger system load p1 c1 source1 v ref v supply figure 7. max4960 typical operating circuit 2
max4959/max4960 high-voltage ovp with battery switchover ______________________________________________________________________________________ 15 6, 8, 10l udfn.eps even terminal l c odd terminal l c l e l a e e d pin 1 index area b e a b n solder mask coverage a a 1 pin 1 0.10x45 l l1 (n/2 -1) x e) xxxx xxxx xxxx sample marking a1 a2 7 a 1 2 21-0164 package outline, 6, 8, 10l udfn, 2x2x0.80 mm -drawing not to scale- package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max4959/max4960 high-voltage ovp with battery switchover 16 ______________________________________________________________________________________ common dimensions symbol min. nom. a 0.70 0.75 a1 d 1.95 2.00 e 1.95 2.00 l 0.30 0.40 pkg. code n e b package variations l1 6 l622-1 0.65 bsc 0.300.05 0.250.05 0.50 bsc 8 l822-1 0.200.03 0.40 bsc 10 l1022-1 2.05 0.80 max. 0.50 2.05 0.10 ref. (n/2 -1) x e 1.60 ref. 1.50 ref. 1.30 ref. a2 - -drawing not to scale- a 2 2 21-0164 package outline, 6, 8, 10l udfn, 2x2x0.80 mm 0.15 0.20 0.25 0.020 0.025 0.035 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max4959/max4960 high-voltage ovp with battery switchover maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. springer 10lumax.eps package outline, 10l umax/usop 1 1 21-0061 rev. document control no. approval proprietary information title: top view front view 1 0.498 ref 0.0196 ref s 6 side view bottom view 0 0 6 0.037 ref 0.0078 max 0.006 0.043 0.118 0.120 0.199 0.0275 0.118 0.0106 0.120 0.0197 bsc inches 1 10 l1 0.0035 0.007 e c b 0.187 0.0157 0.114 h l e2 dim 0.116 0.114 0.116 0.002 d2 e1 a1 d1 min - a 0.940 ref 0.500 bsc 0.090 0.177 4.75 2.89 0.40 0.200 0.270 5.05 0.70 3.00 millimeters 0.05 2.89 2.95 2.95 - min 3.00 3.05 0.15 3.05 max 1.10 10 0.60.1 0.60.1 ? 0.500.1 h 4x s e d2 d1 b a2 a e2 e1 l l1 c gage plane a2 0.030 0.037 0.75 0.95 a1 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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